Verilog array assigned to an other array

Thread starter FboDigit
Start date Jul 18, 2012

Status: Not open for further replies.

Jul 18, 2012

FboDigit

Member level 1

Hi all !

I am currently programming in verilog/systemverilog and I want to know if there is a way to assigne an array to an other!!!

I know that you can not access an entire array and you can not access a slice of an array.
But is there a way to copy a part of an array into an other like this

Code:

task....
     integer array1[7:0];
     integer array2[7:0];
     begin

          array1[3:2] = array2[3:2];

     end
endtask

OR like this

Code:

task....
     integer array1[7:0];
     integer array2[7:0];
     reg [7:0] number
     begin
          number = 3
          array1[number-:1] = array2[number-:1];

     end
endtask

Please help me !!!!

Status: Not open for further replies.

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Verilog array assigned to an other array

FboDigit

Member level 1

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