[SOLVED] Verilog - array and vector access

[pbernardi]

Hello all,

I would like to access part of a vector, in a wire that is also an array. Is it possible somehow?

For example, the example below is not valid (I just make the code now by head, so sorry for any possible inconsistence):

wire [15:0] a[2:0];

genvar i;

for (i=0;i<8;i=i+1)
always @*
begin
  case (a[15:14][i])
  ...
  ...
  endcase
end

while this is valid

wire [15:0] a;

always @*
begin
  case (a[15:14])
  ...
  ...
  endcase
end

is there a way to address this? I know that I cannot access a slice of an array, but I want to access a slice of a vector that is also an array.

 

[ads-ee]

The slice of the vector is last.

case (a[i][15:14])

 

[pbernardi]

Great, just a syntax problem. Thank you.