punj33
Newbie level 6
As a part of my project, I need to interface with DDR SDRAM and I have an IP core of RAM controller. However, my whole project is in Verilog and the ip i got is in VHDL.
So, can a project have both VHDL and Verilog ?
I saw in the forums and learnt about XHDL. How efficient is it? I tried to convert one of the files of the controller but the demo refused to convert citing the file is too large. Are there any free sources or any other alternatives ?
So, can a project have both VHDL and Verilog ?
I saw in the forums and learnt about XHDL. How efficient is it? I tried to convert one of the files of the controller but the demo refused to convert citing the file is too large. Are there any free sources or any other alternatives ?