I tried a simple program where I instantiated vhdl from my verilog code
library ieee;
use ieee.std_logic_1164.all;
entity mainvhdl_en is
port (in1,in2:in std_logic;
out1,out2
ut std_logic);
end entity;
architecture mainvhdl_arch of mainvhdl_en is
begin
out1<=in1 or in2;
out2<=in1 and in2;
end architecture;
module test1(a,b,c,d);
input a,b;
output reg c,d;
mainvhdl_en mainvhdl_en1(.in1(a),.in2(b),.out1(c),.out2(d));
endmodule
Then the error I get in modelsim when i try to simulate the verilog module is :
# ** Fatal: (vsim-3364) Illegal Verilog connection (3rd) for VHDL output port 'out1'.
# Time: 0 ns Iteration: 0 Instance: /test1/mainvhdl_en1 File: vh.vhd Line: 6
# FATAL ERROR while loading design
# Error loading design
do I have to change some settings in modelsim like mixed language sth ?