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Verilog-A simulation error in Virtuoso

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wandoo

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Hi,

I am trying to setup my Cadence Virtuoso (w/ MMSIM) environment and facing with this kind of error when using sth related to Verilog-A in the test schematic.

1669202116183.png


I found some people who had similar issues on google and Cadence support pages,
and tried what's suggested to solve it.

1. In ADE environment options, check "run with 64b" option and and add "-ac 0" user cmdline
-> no effect
2. check tool versions and machine environment
: IC6.1.8-64b.500.24
: MMSIM151.394
: I am on Windows 11 WSL with CentOS 7.9. (if it matters..)
1669202809778.png

1669202940636.png

-> guess everything is running on 64b, tools are new enough

3. export CDS_AHDLCMI_ENABLE=NO
-> no effect

4. and I this log in ahdlcmi.out
1669203333543.png




Any ideas will help!
Thanks in advance.
 

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