veriloga model convergence
Thank you for replying !!
noiseless, qqmz !!
> noiseless
I used idal switch. Nevertheless, there were some errors at certain input voltage values as follows.
>Zero diagonal found in Jacobian at ...<Instance name>
AND
>The values for those nodes did not converce on the last Newton iteration are given below.
>Also given is the manner in which the convergence criteria were not satisfied in the followin form
>
>...<condition equations>
But I couldn't understand what problems were...
And I have to use nonideal switch too from now.
> qqmz
I used spectre simulator.
Now I'm designing Pipeline ADCs. But the cirtcuit scale is extremely large,
so full transistor level simulation can't be impossible.
And I determined to create the model with verilog-A. With the model,
I want to make full simulation possible. And I think nonideal model is required.
So now I want to create the nonideal switch model.
And I used it as well as circuit components (ex. nmos, vdd...)
But there were many errors... I could'nt understand what caused those errors.
I'm creating Pipeline ADC model in the end.
Sorry for my poor English...
Thank you !