Verilog-A problem with DC convergence

[analogman]

Hello!

Now, I am designing a system for swiched-capacitor circuit.
And I am using Verilog-A for switch model.

But simulation isn't running because of DC convergence.
So I am investigating about DC convergence.
How can I solve this problem?

I have read a paper about the problem as follows,

>flipping the switch solves the problem

But I can't understand above message means.
Who can understand above message?
Please tell me in detail.

Thanks..

 

[noiseless]

veriloga switch

There is ideal switch in the cadence lib

 

[qqmz]

verilog-a switch

hi ,what is the simulator you used ? spctre or else ?

 

[qqmz]

variable resistor veriloga

i am design a system which include a pll,so i want to model it in verilog-A, can you tell me how to simulate it using the spectre?

 

[analogman]

veriloga model convergence

Thank you for replying !!
noiseless, qqmz !!

> noiseless

I used idal switch. Nevertheless, there were some errors at certain input voltage values as follows.

>Zero diagonal found in Jacobian at ...<Instance name>

AND

>The values for those nodes did not converce on the last Newton iteration are given below.
>Also given is the manner in which the convergence criteria were not satisfied in the followin form
>
>...<condition equations>

But I couldn't understand what problems were...
And I have to use nonideal switch too from now.

> qqmz

I used spectre simulator.

Now I'm designing Pipeline ADCs. But the cirtcuit scale is extremely large,
so full transistor level simulation can't be impossible.
And I determined to create the model with verilog-A. With the model,
I want to make full simulation possible. And I think nonideal model is required.

So now I want to create the nonideal switch model.
And I used it as well as circuit components (ex. nmos, vdd...)
But there were many errors... I could'nt understand what caused those errors.

I'm creating Pipeline ADC model in the end.

Sorry for my poor English...
Thank you !

 

[uncle_urfi]

+switch +model +(behavioral or verilog-a)

One side of the switch, if left unconnected can give rise to convergence problems.

Also two nodes that are being inadvertently shorted out can create a problem.

It is difficult to answer without more information. Use a voltage variable resistor as a non-ideal switch and configure very high res for open state and very low res for closed state.

 

[noiseless]

create a pulse verilog

I am using spectre.

There are two ways to overcome the DC converge.

1. set initial value at the switch two ends.

2. using pulse voltage as your DC voltage and put the width of the pulse to inf. help it converge.

BTW, please give me your verilog-A code of the switch, is that fine?

 

[analogman]

veriloga model of a switch

Thank you for replying and some good advises!
uncle_urfi, and noiseless.

> uncle_urfi

Thank you.
I'm tring voltage variable resistor as a non-ideal switch.

> noiseless

I tried two ways immediately, and some cases of convergence problems
were resolved. Thank you!

But other cases still have a problem.

My verilog-A code is this.

Basic description of the non ideal switch is from following papers.

> Verilog-A Reference Manual
> E.Lauwers et al "An efficient behavioral model of a CMOS sampling
switch" STW-2000

Simulation using one switch is running.(while output voltage is
differ from the transistor level circuit)
And my programming is poor, so it may be understandable.

Thank you !

 

[mmohsen]

setting dc values in verilog-a

i am design a system which include a pll,so i want to model it in verilog-A, can you tell me how to simulate it using the spectre?

if you still need help in system design using verilog-a just tell me and i will try to help you
and for a start try this link it is very interesting.

https://www.designers-guide.org/VerilogAMS/

regards,..

 

[qqmz]

running verilog a with spectre

mmohsen, thank you , i will need your help someday,