Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog A model of TFET

Status
Not open for further replies.

IntuitiveAnalog

Member level 2
Joined
May 18, 2014
Messages
52
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,684
Hi All,
I am using verilog A model ofTFET from Penn State University which is given below.


Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
`include "constants.vams"
`include "disciplines.vams"
module NTFET(d,g,s);
inout d,g,s;
electrical g,d,s;
real Ids, Cgs, Cgd, Qs, Qd,Qg;
parameter real W=1; //Device width
analog begin
Ids=$table_model(V(d,s), (V(g,s)), "IdVg-NTFET_Lg20nm.tbl","1LL,1LL");
Cgd=$table_model(V(d,s), (V(g,s)), "CGD-NTFET_Lg20nm.tbl","1LL,1LL");
Cgs=$table_model(V(d,s), (V(g,s)), "CGS-NTFET_Lg20nm.tbl","1LL,1LL");
if(analysis("dc")) begin
 I(d,s) <+ 1*Ids*W;
end
else begin
 
if(analysis("tran")) begin
 Qd = (-1*W*Cgd)*(V(g,d));
 Qs = (-1*W*Cgs)*(V(g,s));
 Qg=-1*(Qd+Qs);
 I(d,s) <+ 1*Ids*W ;
 I(d) <+ ddt(Qd);
 I(s) <+ ddt(Qs);
 I(g)<+ ddt(Qg);
 end 
end
end
endmodule



If anybody could help me in ac analysis from this model , I ll be thankful to him/her.

Thanks
 
Last edited by a moderator:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top