cnd9
Newbie level 2
Hi,
I'm running verilog-a for the first time and trying to get the following code to work:
etc.....
The behavior I want to see is, "sIntegral" starts at 0.5 and (if V(bj) is negative), keeps decreasing until int(Vdt) becomes less than zero, at which point I want the integration to stop.
Instead, "integrand" initializes to zero, sIntegral initializes to 0.5, and neither change in the simulation as verified with the strobe statements (even though there is definitely a voltage present).
How can I make the conditional statement re-evaluate at each time step so that the integral/integrand will update?
thank you!
I'm running verilog-a for the first time and trying to get the following code to work:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 analog begin if (sIntegral > 0) integrand = V(bj); else integrand = 0; sIntegral = idt(integrand,.5); $fstrobe(fprt,"%f", integrand); $fstrobe(fprt,"%f", sIntegral);
etc.....
The behavior I want to see is, "sIntegral" starts at 0.5 and (if V(bj) is negative), keeps decreasing until int(Vdt) becomes less than zero, at which point I want the integration to stop.
Instead, "integrand" initializes to zero, sIntegral initializes to 0.5, and neither change in the simulation as verified with the strobe statements (even though there is definitely a voltage present).
How can I make the conditional statement re-evaluate at each time step so that the integral/integrand will update?
thank you!
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