Verification using E language

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tiger_shark

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Hello all,

Could anyone please help me with regard to which software I can use to do E programming for Verilog design verification? I konw that Spaceman Elite is the one but it does not seem to have a demo / free version or ... . Is any free tool availabe? I am reading the book "Design verification with E" and I want to do its examples... . What other tools I can use?

Thank you

Tiger-Shark
 

Hello Tiger-Shark

there is no demo software available for the Free. ucan ask in u r college. so they can buy it with nominal fee.
Thanks
rameshs
 

Hi there, could U give some info about which verification language used in the big company ?
 

System Verilog for verification and ABV.
SystemC for architecture modelling,
Specman , Vera for verification.
 

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