Verification test sequence Vs Chip start sequence !

[kamalkundu]

I am working on micro-controller verification where we are using assembly (for processor) and verilog to give stimuls or probe the value.

When somebody asks me about verification test sequence.I come-up with answer that :
1) Chip is power up and power on reset is de-asserted.
2) Reset sequence starts a) reset de-asserted b) oscillator started c) oscillator calibrated.
3) Calibration values etc are loaded from nvm.
4) Reset vector is passed to processor and boot sequence is executed.
5) Assembly of by testcase started with stimulus.

Am i missing anything ? or verification test sequence is completely different thing ?:-(

 

[dftrtl]

Verification sequence is to traget an functionality.
Chip start sequence is Functionality sequence.