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verification in VLSI

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engnr.abhinav

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how many types of verification in VLSI design and what is the difference between them
 

Serfacy

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The basic ones are:
1. DRC- design rule check - it checks geometrical rules of drawn layers
2. ERC - electrical rule check - it checks electrical issues, e.g. shorts, unconnected nets (it is usually done together with LVS)
3. LVS - layout versus schematic - compares if layout corresponds to schematic (it compares graphs taken from schematic netlist and netlist after nominal extraction)
4. spice simulations using at first schematic, but also after nominal and full (CC and RC) extraction
 

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