Verification for newbie

[Jennis]

Hello Friend,

I've been working on ASIC flow (e.g. synthesis, sta, dft, pnr), for my next project i'll be involved in design verification. I've no experience in this field. Could anybody give some idea how to start. I will be working on digital simulator VCS using verilog language. Is there any book or material which can give good starting point or any guidelines for creating verification model?

Any kind of suggestion will be highly appreciated.

 

[tariq786]

Hi

I think you should master the verilog language to your best and then systemverilog for verification. These will prepare your basis.

Hope it helps.

 

[shanmugaveld]

Check WWW.TESTBENCH.IN where you can understand verification concepts

 

[ljxpjpjljx]

you need to know about OOP methodology and familiar with C/C++/SV/SC language to better verify DUT!

 

[gck]

Hi,

Here is book, I would like suggest,
Writing testbenches: functional verification of HDL models
By Janick Bergeron

Verification is an art. Thinking process for verification is way different than design. This book has helped me lot for switching between Design to Verification.
You atleast make sure you read Chap 2. That will give you idea, what to look for.

 

[blooz]

SystemVerilog for Verification, second edition Chris Spear
This book is an introduction to the testbench features of the SystemVerilog language. It is meant for anyone who knows basic Verilog (1995) and needs to verify a design. It includes over 400 examples


h**p://chris.spear.net/systemverilog/