Dec 15, 2010 #1 P paavithra Banned Joined Dec 14, 2010 Messages 22 Helped 4 Reputation 8 Reaction score 4 Trophy points 1,283 Location bangalore Activity points 0 What is the role of Design Verification in verification design flow.
Dec 15, 2010 #2 ckshivaram Advanced Member level 6 Joined Apr 21, 2008 Messages 5,060 Helped 2,150 Reputation 4,306 Reaction score 2,088 Trophy points 1,393 Location villingen (Germany) / Bangalore Activity points 30,086 **broken link removed** http://cc.ee.ntu.edu.tw/~ywchang/Courses/EDA04/lec1.pdf http://www.cs.umbc.edu/~cpatel2/links/315/lectures/chap1_lect00_intro.pdf
**broken link removed** http://cc.ee.ntu.edu.tw/~ywchang/Courses/EDA04/lec1.pdf http://www.cs.umbc.edu/~cpatel2/links/315/lectures/chap1_lect00_intro.pdf
Dec 17, 2010 #3 P paavithra Banned Joined Dec 14, 2010 Messages 22 Helped 4 Reputation 8 Reaction score 4 Trophy points 1,283 Location bangalore Activity points 0 thank you sir
Dec 28, 2010 #4 P paavithra Banned Joined Dec 14, 2010 Messages 22 Helped 4 Reputation 8 Reaction score 4 Trophy points 1,283 Location bangalore Activity points 0 hello sir, i am not able to download information from this link http://cc.ee.ntu.edu.tw/~ywchang/Courses/EDA04/lec1.pdf please help
hello sir, i am not able to download information from this link http://cc.ee.ntu.edu.tw/~ywchang/Courses/EDA04/lec1.pdf please help
Dec 29, 2010 #5 L ljxpjpjljx Advanced Member level 3 Joined May 5, 2008 Messages 968 Helped 80 Reputation 162 Reaction score 56 Trophy points 1,308 Location Shang Hai Activity points 4,679 you need to do RTL/Gate level simulation in system level!