May 10, 2006 #1 D davyzhu Advanced Member level 1 Joined May 23, 2004 Messages 494 Helped 5 Reputation 10 Reaction score 2 Trophy points 1,298 Location oriental Activity points 4,436 Hi all, I found that some verification procedure using Non-HDL such as C++/Java. But how these Non-HDL language generate edge stimulus? Can Non-HDL also generate @posedage??? Is there any basic idea behind it? Best regards, Davy
Hi all, I found that some verification procedure using Non-HDL such as C++/Java. But how these Non-HDL language generate edge stimulus? Can Non-HDL also generate @posedage??? Is there any basic idea behind it? Best regards, Davy
May 10, 2006 #2 A aji_vlsi Advanced Member level 2 Joined Sep 10, 2004 Messages 643 Helped 85 Reputation 170 Reaction score 12 Trophy points 1,298 Location Bangalore, India Activity points 4,944 davyzhu said: Hi all, I found that some verification procedure using Non-HDL such as C++/Java. But how these Non-HDL language generate edge stimulus? Can Non-HDL also generate @posedage??? Is there any basic idea behind it? Best regards, Davy Click to expand... Hi Davy, Take a look at TEAL http://teal.sf.net for one such approach. I would however recommend you to look at SystemVerilog instead. Regards Ajeetha, CVC www.noveldv.com
davyzhu said: Hi all, I found that some verification procedure using Non-HDL such as C++/Java. But how these Non-HDL language generate edge stimulus? Can Non-HDL also generate @posedage??? Is there any basic idea behind it? Best regards, Davy Click to expand... Hi Davy, Take a look at TEAL http://teal.sf.net for one such approach. I would however recommend you to look at SystemVerilog instead. Regards Ajeetha, CVC www.noveldv.com
May 11, 2006 #3 D davyzhu Advanced Member level 1 Joined May 23, 2004 Messages 494 Helped 5 Reputation 10 Reaction score 2 Trophy points 1,298 Location oriental Activity points 4,436 Hi Ajeetha, Thank you I have take a look at TEAL and wish to gain some idea. Does SystemVerilog use some techniques other than PLI? Best regards, Davy
Hi Ajeetha, Thank you I have take a look at TEAL and wish to gain some idea. Does SystemVerilog use some techniques other than PLI? Best regards, Davy
May 11, 2006 #4 A aji_vlsi Advanced Member level 2 Joined Sep 10, 2004 Messages 643 Helped 85 Reputation 170 Reaction score 12 Trophy points 1,298 Location Bangalore, India Activity points 4,944 davyzhu said: Hi Ajeetha, Does SystemVerilog use some techniques other than PLI? Best regards, Davy Click to expand... Lots and lots... read SV LRM or my SNUG 06 paper for some references. Ajeetha, CVC www.noveldv.com
davyzhu said: Hi Ajeetha, Does SystemVerilog use some techniques other than PLI? Best regards, Davy Click to expand... Lots and lots... read SV LRM or my SNUG 06 paper for some references. Ajeetha, CVC www.noveldv.com
May 12, 2006 #5 maxsnail Member level 5 Joined Sep 29, 2004 Messages 85 Helped 6 Reputation 28 Reaction score 1 Trophy points 1,288 Activity points 584 when two language cosimulation, the communication is through systemcall,and VPI, delay or posedge can be implemnet in both simulator
when two language cosimulation, the communication is through systemcall,and VPI, delay or posedge can be implemnet in both simulator
May 13, 2006 #6 omara007 Advanced Member level 4 Joined Jan 6, 2003 Messages 1,237 Helped 50 Reputation 102 Reaction score 16 Trophy points 1,318 Location Cairo/Egypt Activity points 9,716 You need to check things like SystemC, E, and Vera .. You can also try tools like ModelSim or CCSS to verify an HDL block using SystemC for example ..
You need to check things like SystemC, E, and Vera .. You can also try tools like ModelSim or CCSS to verify an HDL block using SystemC for example ..