Vera to System Verilog

[vantage]

Dear members, What are the similarities between Vera and System Verilog .
And
How easy is such a transition , Have anyone experienced such a transition at their work.

Details will be very much appreciated.

Thanks

 

[mssajwan]

Hi
They almost work on the same framework.
synopsys is promoting SystemVerilog at the moment.

Not much changes need to be done. once you are familiar with vera transition will be easy.

regards
Manmohan

 

[rajkishore12345]

It depends only on the vendors.. by function both have their own advantages .....

 

[edacw1]

Vera is only for verification but SV is for design not only verification.

 

[darylz]

synopsys donate some IP of vera to SV...

 

[zhangpengyu]

both like C/C++.
systemverilog is good for persion in hardware background.
while vera is good for persions in software background.

 

[niko_zhang]

Try this tools <url>www.veriez.com</url>

 

[vinod_cheedella]

if you are working only on verification side,
means you are always writing test bench prorams, then vera is ok,

if you do write both the design and test benches,
it better to adopt the system verilog.

you can have design as well as test bench constructs in system verilog.

i feel, nothing to worry in this transition from vera to SV,
syntax wise, very few differences are there, its not a problem.
and the constructors are very similar except a few...

people who do verification even from C/C++, they like vera,
because, syntax wise vera is simple for them.

But, those who spend time mostly in vhdl/verilog side, would like to work on SV side...

I strongly believe that, once you moved into SV,
you will never go back to your VERA....
and transition also does't take much time...