if you are working only on verification side,
means you are always writing test bench prorams, then vera is ok,
if you do write both the design and test benches,
it better to adopt the system verilog.
you can have design as well as test bench constructs in system verilog.
i feel, nothing to worry in this transition from vera to SV,
syntax wise, very few differences are there, its not a problem.
and the constructors are very similar except a few...
people who do verification even from C/C++, they like vera,
because, syntax wise vera is simple for them.
But, those who spend time mostly in vhdl/verilog side, would like to work on SV side...
I strongly believe that, once you moved into SV,
you will never go back to your VERA....
and transition also does't take much time...