Vector assignment in Verilog?

davyzhu · Jan 25, 2007

verilog vector assignment

Hi all,

Is there Vector assignment in Verilog like C show below:
reg [31:0] vectors [2:0] = {5, 6, 7};
Or I have to assign vectors one by one?

Best regards,
Davy

nand_gates · Jan 25, 2007

verilog vector assignment module

At the best you can do this...

Code:

module vec_assign();
   reg [31:0] vectors [2:0];

initial 
  {vectors[2], vectors[1], vectors[0]} = {32'd5, 32'd6, 32'd7}; 

endmodule // vec_assign

Vector assignment in Verilog?

davyzhu

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Vector assignment in Verilog?

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