hwb
Newbie level 5
Hi folks,
For a FPGA-based digital audio design I need a clocking circuit which eliminates jitter from a recovered 64fs (3.072 MHz) S/PDIF clock and multiplies it by 16 for getting a clean 1024fs master clock. Cycle-to-cycle jitter may not exceed 80ps.
Now I have the problem of finding suitable ICs for this task. The usual audio clock generator ICs like PLL170X derieve the clocks from a 27MHz crystal and have no external reference clock input. Also, they do not provide 1024fs.
Comms clocking ICs like the MK2049-45A are going into the right direction, but have the wrong frequency ranges.
More versatile ICs like a MK2069-02 provide the needed features but are way too big.
I want to avoid using multiple ICs for VCXO jitter elimination and clock multiplication if possible, so does anyone have a suggestion for an integrated solution? Perhaps there are some ICs with the possibility of using external dividers within the VCXO/PLL loop allowing me to set frequency relation with a divider in the FPGA?
Any hints are welcome!
Regards,
Holger
For a FPGA-based digital audio design I need a clocking circuit which eliminates jitter from a recovered 64fs (3.072 MHz) S/PDIF clock and multiplies it by 16 for getting a clean 1024fs master clock. Cycle-to-cycle jitter may not exceed 80ps.
Now I have the problem of finding suitable ICs for this task. The usual audio clock generator ICs like PLL170X derieve the clocks from a 27MHz crystal and have no external reference clock input. Also, they do not provide 1024fs.
Comms clocking ICs like the MK2049-45A are going into the right direction, but have the wrong frequency ranges.
More versatile ICs like a MK2069-02 provide the needed features but are way too big.
I want to avoid using multiple ICs for VCXO jitter elimination and clock multiplication if possible, so does anyone have a suggestion for an integrated solution? Perhaps there are some ICs with the possibility of using external dividers within the VCXO/PLL loop allowing me to set frequency relation with a divider in the FPGA?
Any hints are welcome!
Regards,
Holger
