delon
Junior Member level 2
Hello,
I have a src code in VHDL and tb in verilog. I am doing the following to compile:
vhdlan vhdmodule.vhd
vcs verilog_tb.v
However for the second one, its saying that "Module definition of above instance is not found in the design." Looks like it can't recognize the vhdl module instantiated in the TB. Can anyone please help me out with this? How does the flow works?
I have a src code in VHDL and tb in verilog. I am doing the following to compile:
vhdlan vhdmodule.vhd
vcs verilog_tb.v
However for the second one, its saying that "Module definition of above instance is not found in the design." Looks like it can't recognize the vhdl module instantiated in the TB. Can anyone please help me out with this? How does the flow works?