fly_fish
Junior Member level 3
simalated
I have designed a dual-band VCO in charted RF 0.18um CMOS 1P6M process.The VCO's measured frequency is lower than the simalated freauency. The differency is 100MHz. This results my PLL circuit can't lock. ps: The VCO 's mid-frequency is 1.2G/1.5G. Also, I have extracted R-C parameter from the VCO layout.
Anyone knows the reason?
Another question: how to design a test circuit to verify the new IC process's parameter?
I have designed a dual-band VCO in charted RF 0.18um CMOS 1P6M process.The VCO's measured frequency is lower than the simalated freauency. The differency is 100MHz. This results my PLL circuit can't lock. ps: The VCO 's mid-frequency is 1.2G/1.5G. Also, I have extracted R-C parameter from the VCO layout.
Anyone knows the reason?
Another question: how to design a test circuit to verify the new IC process's parameter?