VCO linearity verification??

[faizalism]

linear vco

Hi,

How to verify the VCO linearity?? Can we simply see the graph (f vs Vcontrol)? Because last time I presented my works, one of the engineer told me that we can't verified it by using naked eye. He said, there is technique to verify it, by using matric/matrix?? Do you have any links mentioned about it??

Thanks,

 

[shwoo]

Agilent sells very nice piece of equipment.
Look for E5052 or older model 4352B.
Very expensive. $81K.
But you can perform a rough measurement with ordinary test
equipment. Have you tried to tune the VCO by a lab power supply?

S. H.

 

[FvM]

Necessity of an explicite verification obviously depends on the specfication. For usual requirements, the linearity may be guaranteed by design. Also the verification effort depends on the required accuracy.

 

[AdvaRes]

Necessity of an explicite verification obviously depends on the specfication. For usual requirements, the linearity may be guaranteed by design. Also the verification effort depends on the required accuracy.

Hi all,

Is it necessary to have a linear VCO ?
Could we use PLL using non linear VCO (see figure) ?

 

[Miguel Gaspar]

You can use he line adjust technique that gives you the best line and the dispersion factor.

 

[FvM]

Could we use PLL using non linear VCO (see figure) ?

A VCO behaving with a non-monotonic characteristic as in your figure wouldn't be suitable for a PLL, also large gain variations are probably unwanted, but high linearity isn't necassary for PLL applications of VCO. It may be required for other applications.

 

[jecyhale]

Necessity of an explicite verification obviously depends on the specfication. For usual requirements, the linearity may be guaranteed by design. Also the verification effort depends on the required accuracy.

Hi all,

Is it necessary to have a linear VCO ?
Could we use PLL using non linear VCO (see figure) ?

I think VCO must be linear with Vtune, or else it can't be locked.

 

[RF-OM]

Your plot shows a good possibility of some parasitic effects in the circuit. As result self resonances are possible. You need to check very carefully all components and their respective self-resonance frequencies (SRF). It may be too long connecting traces or too big SMT components with low SRF, via effect or something like this. Definitely such characteristic of VCO as your plot shows is unacceptable.

Best regards,
RF-OM