[SOLVED] VCO different o/p frequencies

[Engineer4ever]

Hi,

I designed a 5-stage VCO using maneatis delay cell to produce ten spaced clocks at 1.6GHz. The problem is, the output clocks don't have the same frequency, there is a difference that ranges between 60~90 MHz between each two clocks. How is that possible? The five cells are replica of each other with the same sizes and biasing.

Thanks,

 

[KlausST]

Hi,

I assume it is some kind of interference, where two clock sources in close proximity to each other tend to influence each other.

But I have no idea how much this can influence the resulting frequency.
In any case this will cause a lot of jitter.
Can you perform a jitter test?

Klaus

 

[dick_freebird]

In a ring oscillator you can't have different
frequencies at different tap-points, without
it being really messed up. Maybe this is some
sort of measurement artifact. The error you
state, is 4-6%. Excessive phase noise might
be spoofing the frequency measurement
method. Eyeball the jitter relative to period
(bearing in mind that trying to measure, can
introduce more, especially if you did not foresee
the need to buffer those clock phases for test).
Adding probe loading to one phase could jack
the frequency around by how the current is
returned to the ground point and the ring nodes.
Suggest you load them all equally with some sort
of high-Z-to-50-ohm dividers that have minimum
added C, such that attaching one more probe (or
coax length) is seen to not affect fOsc.

 

[KlausST]

Hi,

if it is a single true ring oscillator, then dick_freebird is correct.

My answer refers to multiple independent oscillators.

Klaus