VCO design -- NEGATIVE Kvco

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steadymind

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Hi guys,

I designed a ring VCO to work from 1G to 3.6GHz but as I increase my control voltage my VCO freq decreases. Some papers i referred after my design report that freq increases as control voltage increases.

Does this mean my Kvco is NEGATIVE.... Is it wrong ?

Please Explain

Thanks
 

As each PLL works as a control loop the sign of the loop gain (gain of the open loop) must be negative (one or three minus signs within the loop).
It is no problem when your Kvco is already negative as long as you introduce no other phase shift of 180 deg. within the loop.

Added after 2 minutes: It is quite normal that there is a negative sign by combining both signals at the PD. In this case, you have to introduce a third phase reversal anywhere within the loop.
 

I am yet to finish my PLL and i have done only the VCO so far. So could i end up with problems ??
 

There wont be any issues as long as it is remembered and taken care before closing the loop. It is normal to have a negative KVCO.
 

Whatever negative or positive, the only important thing is that the kvco vs control voltage is monotonic.
 

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