VCO design and measurement

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STOIKOV

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hello! I designed a ring vco, simulated and did its layout. Then I simulate the extracted circuit (LEdit) and simulated again to obtain a frequency against control voltage curve. So the chip was fabricated and the experimental results show that the oscillation frequency is about 15 or 20% above the simulation frequency.

I hoped to obtain in lab a frequency below the simulated, maybe due to other parasitics not considered, but the frequency measured is larger.

Is this a normal behavior ? How can I justificate this percent of error. I was thinking on process variations, what do you think ?
 

hi,
maybe it is a fast process. and you can check the ckt by simulating the ring osc ckt in fast corner.

good luck
jeff
 

    STOIKOV

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what means simulate in "fast corner" ?
 

I'm using a Mosis process, the fast model is a simulator option or a complete model like level=49 that currently am using ?
 

It's a complete model.

STOIKOV said:
I'm using a Mosis process, the fast model is a simulator option or a complete model like level=49 that currently am using ?
 

    STOIKOV

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I want design a ring oscillator,can you provide me some tutorial by ADS. and i want to know how can i builde the MOS component i need,and my operated frequency is about 5GHz!thank you!
 

henryhd said:
I want design a ring oscillator,can you provide me some tutorial by ADS. and i want to know how can i builde the MOS component i need,and my operated frequency is about 5GHz!thank you!

I think that there're built-in samples for ring osc in ADS.. look for them..
 

thank you and i'll try it !
 


take a look at the temperature difference between simulation and silicon.
vco frequency is sensitive to temperature.
 

    STOIKOV

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that your layout is well match?
 

    STOIKOV

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