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VCO Control Voltage variation in PLL

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Debdut

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I have created an integer and fractional PLL.
The integer PLL is locking fine. The fractional PLL has a delta-sigma modulator which varies the feedback frequency divider modulus. Maybe that's why the control voltage on the VCO is varying periodically?
Is there a way to mitigate the periodic variation of control voltage of the VCO in fractional PLL?
 

Hi,

i guess your fractional part creates phase jitter. Because the phase deviation is used to generate the VCO control voltage it might the cause for the periodically change..

Usually a PLL is made with two integer divider stages. One at the input (D), the other in the feedback path.
Because it is in the feedback it acts like a multiplier (M).

So f_out = f_in * M / D

with this you are able to create a lot of frequencies, but it seems you need something special.. or why did you do the fractional (divider) PLL.

Klaus
 

Thanks Klaus for replying.
Is the input divider mandatory?
I need a channel spacing of 300 kHz in the band of 402-405 MHz. So creating a integer N synthesizer will require ref frequency of 300 kHz and divider ratio of 1340 - very high. Also for such a low ref frequency the loop BW will be also low, the locking time will also be high.
In fractional PLL I set the ref frequency 6 MHz and frequency division ratio to vary between 67-68, much larger bandwidth, smaller settling time, etc.

So, about my problem "Is there a way to mitigate the periodic variation of control voltage of the VCO in fractional PLL?"
 

I have created an integer and fractional PLL.
The integer PLL is locking fine. The fractional PLL has a delta-sigma modulator which varies the feedback frequency divider modulus. Maybe that's why the control voltage on the VCO is varying periodically?
Is there a way to mitigate the periodic variation of control voltage of the VCO in fractional PLL?

As I recall HP solved this in one of their generators using a phase counter, DAC, an integrator and S&H detector to inject an equal and opposite sawtooth in the VCO feedback loop for each missing or extra pulse in the fractional loop to null the periodic variation. circa 1977.

They used an integer PLL with 1MHz increments and fractional PLL with 6 or 8 digit resolution within 1MHz to synthesize any frequency for a 2 loop system
 

Is this method called "calibration of PLL"?
I went through Razavi's book, there is a similar description on reduction of quantization noise in VCO output using DAC in a feed-forward path, but the author states that it is difficult to match the phases of the control voltage and DAC output. If you can't match the phases the result will be a backlash.
Also, is this process dependent on PVT?
 

So, about my problem "Is there a way to mitigate the periodic variation of control voltage of the VCO in fractional PLL?"
Yes, by reducing the loop filter bandwidth.
 

How is the loop filter bandwidth related to the delta-sigma modulus variation that is causing the variation of VCO control voltage?
 

It believe it can be derived from SD noise shaping characteristics.
 

I think there is no relationship between loop BW and SD noise shaping.
I think that more the loop BW, more amount of quantization noise will be allowed inside the BW.
 

Is this method called "calibration of PLL"?
I went through Razavi's book, there is a similar description on reduction of quantization noise in VCO output using DAC in a feed-forward path, but the author states that it is difficult to match the phases of the control voltage and DAC output. If you can't match the phases the result will be a backlash.
Also, is this process dependent on PVT?

No it is a method to eliminate sawtooth ripple V in fractional N method reported by HP in 1977. Each fraction pulse induces a sawtooth phase error which is averaged to obtain f. Thus VCO ripple can be reduced by injecting integrating pulse of opposite polarity expected while average DC difference is maintained.
- - - Updated - - -

TI discuss modern methods starting page 30
https://www.ti.com/lit/an/swra029/swra029.pdf
 

No it is a method to eliminate sawtooth ripple V in fractional N method reported by HP in 1977. Each fraction pulse induces a sawtooth phase error which is averaged to obtain f. Thus VCO ripple can be reduced by injecting integrating pulse of opposite polarity expected while average DC difference is maintained.

OK thanks, I'll look into it.
 

I think that more the loop BW, more amount of quantization noise will be allowed inside the BW.
Obviously. But how do you calculate the VCO jitter for a specific bandwidth?

I think there is no relationship between loop BW and SD noise shaping.
No relationship? The noise shaping characteristic describes the spectral distribution of quantization noise.
 

But how do you calculate the VCO jitter for a specific bandwidth?

The VCO is going to mimic the ref frequency within the BW, e.g. if the BW is 1 MHz, then the VCO phase noise characteristics is going to mimic the phase noise characteristics of the up-scaled version of the ref frequency within 1 MHz BW around the VCO frequency (+ some quantization noise) and outside the 1 MHz BW it will reproduce its own phase noise characteristics (+ some quantization noise ??)

The noise shaping characteristic describes the spectral distribution of quantization noise.

The noise is shaped by the delta-sigma modulator, not the loop filter.
 

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