VCO CMOS design issue with phase noise

[Denys]

Hallo, all!

I design VCO 10-12 GHz + div by2 CMOS 0.13 um technology. I use cross-coupled structure. I have a big problen with phase noise. Increase inductance have absolutly no influence on the noise. I have all time -45 dBc/Hz on 10 kHz and -110 dBc/Hz on 1 MHz. I need to have -70 dBc/Hz on 10 kHz and -120 dBc/Hz on 1 MHz.

Sombody can help me.

Thank for all.

 

[khouly]

Re: VCO CMOS Design

what about supply , and filker noise filters
and the sizing of the varactors , and the tail current devices

check them

khouly

 

[pfd001]

VCO CMOS Design

u can increase the amplitude of the VCO

 

[davidwong]

Re: VCO CMOS Design

for a given bias current, phase noise increases with an increasing L in the voltage-limited regime.
for a given inductance L, phase noise increases with the bias current in the voltage-limited regime.
thus try to decrease bias current and inductance

 

[Denys]

Re: VCO CMOS Design

what about supply , and filker noise filters
and the sizing of the varactors , and the tail current devices

check them

khouly

CMOS 0.13 um 1.5 V technology. I have VCO supply by 0.9 - 1.3 V, use tail current devices, and for the filker noise filters I use just capacitor for the fltering second harmonic. I cant use second inductance(for the filtering tail current) because I have area limitation.
I use like varactors n-channel MOS transistor and like swich-capacitors p-channel MOS. Size of NMOS 60/0.13 um and PMOS 80/0.12 um each from 3. (I have 3 PMOS swich-capacitors )

Added after 4 minutes:

and more one problem, when I connect VCO to Divider by 2, Phase noise (flicker 1/f**3) staying worse on 20 dBc/Hz. What is it can be?

 

[khouly]

Re: VCO CMOS Design

is there a varactors in ur design kit , so u can use
and try to use PMOS devices


khouly

 

[agaurav]

Re: VCO CMOS Design

Since there is no change in your phase noise when you change the inductor, the major contribution must be coming form your bias/current-sources which is quite possible at low frequency as 10KHz. For higher frequency, please check if the varactor or cross-coupled load is the major contributor. Thsi way you can focus on the main contributors instead of just playing with inductor.

 

[Denys]

Re: VCO CMOS Design

Since there is no change in your phase noise when you change the inductor, the major contribution must be coming form your bias/current-sources which is quite possible at low frequency as 10KHz. For higher frequency, please check if the varactor or cross-coupled load is the major contributor. Thsi way you can focus on the main contributors instead of just playing with inductor.

Looks like you are right. I have noisy in cross-coupled pair. Can you suggest to me somethink to improve noise in this situation?

 

[rficd]

Re: VCO CMOS Design

you can use pmos only.