Well, here's an example.
I once had to design about 40Kgates of logic for what
was basically a SERDES, part of a spooky satellite fiber
optic bus. To get 400MHz chip scale clock in 0.5u CMOS
(and solve some space related issues) the existing
standard cell library had to be discarded (DFFs could
not even self-toggle at that speed, let alone with any
interstage logic) and all gates designed anew, and the
functional / timing info was provided by the customer
as vcd format files for the stimulus and the "expect"
vectors. I got them to produce me vcd single-bit files,
many of them, one per pin from their Mentor system.