[SOLVED] VC707 clock generation

[Ringkle]

On Xilinx VC707 board, I choose a LVDS 200 MHz system clock provided by a fixed frequency oscillator, which connect to FPGA pins E19 and E18.

But there is no clock signal input to the FPGA, ie, there is no clock source when I implement my design.

How can I make this system clock work?

If anyone know please help. Example design or links may helpful.

https://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf Page29

Thanks
Ringkle

 

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But there is no clock signal input to the FPGA, ie, there is no clock source when I implement my design.

What do you mean by this? Are we supposed to guess what you did in your code?

Instead of asking for someone to post an example design post your code that doesn't work.

If I had to guess...you probably didn't instantiate an ibufgs for that differential clock.

 

[Ringkle]

What do you mean by this? Are we supposed to guess what you did in your code?

Instead of asking for someone to post an example design post your code that doesn't work.

If I had to guess...you probably didn't instantiate an ibufgs for that differential clock.

Thanks for your reply.

To verify the clock source, I just apply the 200 MHz clock to a frequency divider to drive a led, with IBUFGDS , but it doesn't work. I'm a beginner of VC707, are there any key points I missed?