library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rc5round is
port (
si : in std_logic_vector(31 downto 0); -- subkey
di : in std_logic_vector(63 downto 0); -- data in
do : out std_logic_vector(63 downto 0); -- data out
clk : in std_logic -- clk
);
end rc5round;
architecture Behavioral of rc5round is
component addsub
port ( a , b : in std_logic_vector (31 downto 0);
encdec : in std_logic;
c : out std_logic_vector (31 downto 0));
end component;
component circularshift
port (
sn : in std_logic_vector(5 downto 1);
di : in std_logic_vector(31 downto 0);
encdec : in std_logic ;
do : out std_logic_vector(31 downto 0)
);
end component;
component dff
port( d : in std_logic_vector (31 downto 0);
clk : in std_logic;
q : out std_logic_vector (31 downto 0)
);
end component;
component mux2b1
port ( d1 : in std_logic_vector (31 downto 0);
d2 : in std_logic_vector (31 downto 0);
encdec: in std_logic;
dout : out std_logic_vector (31 downto 0)
);
end component;
component xrgate
port ( a ,b : in std_logic_vector (31 downto 0);
c : out std_logic_vector (31 downto 0));
end component;
signal dr,dl : std_logic_vector(31 downto 0);
signal da,cs : std_logic_vector(31 downto 0);
signal m1,xo : std_logic_vector(31 downto 0);
signal m2,ao : std_logic_vector(31 downto 0);
signal cs,m3 : std_logic_vector(31 downto 0);
begin
dl <= di(63 downto 32);
dr <= di(31 downto 0);
d1: dff port map ( dr, clk, dl );
d2: dff port map ( dl, clk, da );
m1 : mux2b1 port map ( cs, da, encdec ,m1 );
m2 : mux2b1 port map ( ao, xo, encdec ,m2 );
m3 : mux2b1 port map ( da, cs,encdec ,m3 );
m4 : mux2b1 port map ( xo, ao, encdec ,dl );
x1 : xrgate port map ( dl,m1,xo );
a1 : addsub port map (m3, si, encdec, ao);
c1 : circularshift port map (dl(4:0), m2, encdec, cs);
end Behavioral;