[SOLVED] various clock generators for testbench, some don't work

Hi,
I'm having a very strange problem with Active HDL. Dunno if it's only in Active, or maybe other simulators, cause this is the only one I got...
I'm writing a simple clock generator for a testbench for simulation.
I've tried 4 different methods. All should return the same clock, right (well, they're pretty straight forward...):

Clock generator 1:

iclk <= (not iclk) after 10ns;

Note: works fine.

Clock generator 2:

iclk <= '0' when (iclk = '1') else '1' after 10ns;

Note: doesn't work. Outputs '0'.


Clock generator 3:

process (iclk)
begin
if iclk = '1' then
iclk <= '0';
else
iclk <= '1' after 10ns;
end if;
end process;

Note: not working. this is the same code as Clock generator 2, just wrote it different (inside a process. Clk Gen 2 isn't inside a process).

Clock generator 4:

process
begin
iclk <= '0';
wait for 10ns;
iclk <= '1';
wait for 10ns;
end process;

Note: working fine.

So, my problems are with generators 2 & 3. Both output iclk of '0'.
Signal iclk is defined:
signal iclk : std_logic:='0';


Any ideas?
Is it Active HDL bug, or some silly mistake of my own?
Any help will do...
Thx!
Tom

For generators 2 and 3, why don't you use "after 10ns" together with "iclk <= '0' " ?
You only have it for "iclk <= '1' "

ok... silly me... working now. Thank you!!!
I suspected it was something stupid.