I wish to make a custom pulse pattern (see attachment). Typically the first bit should have larger duty cycle compare to the following bits. Also the following bits are random in nature...
I could write the code for making a random sequence. Could you please help me writing the addendum first bit?!
If the pulse width of the initial value is random in width then algorithmically you want to use the language's random function, i.e in Verilog $random, and perform the following operation: