This code must be added to each Verilog testbench in order for a VCD file to be generated.
// The following code will generate a VCD file containing
// all of the nets in the instance t.uut. "t" is the module name of the
// testfixture, "uut" is the instance name
// of the design being tested.
initial begin
$dumpfile("invchn26.vcd"); // Change filename as appropriate.
$dumpvars(1, t.uut);
end
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For VHDL simulations, the commands to generate a VCD file must be entered interactively, or contained in a do file.
vcd file my_design.vcd
vcd add testbench/uut/*
This technique will work for both VHDL and Verilog in ModelSim.
Note: When creating a VCD file using the NC simulator, the command must include the -f switch.
The above lines generate a VCD file called my_design.vcd. The entity name of our testbench is testbench and the instance name of the unit under test is uut.
Using the -r switch with ModelSim's vcd add command, or specifying a number of levels other than 1 to the $dumpvars Verilog task will result in a large but significantly more accurate VCD file. Using the -r switch is highly recommended.
VCD files can grow quite large for larger designs, or even for smaller designs if the simulation run time is long enough. Using a VCD file to set the activity rates of signals in XPower may not be an efficient method for certain types of designs, e.g. watchdog timers.
XPower will only read a VCD file up until the first break in the simulation, or vcd off command. After this a warning message will be issued and all data following the vcd off or $dumpoff command in the VCD file will be ignored.
For more information on generating a VCD file from ModelSim, see section 9 of the ModelSim Xilinx User's Manual.