Validation: Creating command structures using System Verilog

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casey480

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I have a DUT with two interfaces, and similar commands can be executed on each.

cmd_int_a would have a different opcode than cmd_int_b, but the same payload and net effect. How can I efficiently abstract this and write a test which can run on either interface? Use a function to translate it? A struct?
 

Re: Validation: Creating command structures using System Ver

have you tried out virtual interface ?
 

Re: Validation: Creating command structures using System Ver

If your DUT has 2 similar bus(interface) you can create 1 SV interface module and instantiate it 2 times in your testbench. Then you can refer to each ether using instance names or you can use SV virtual interfaces.
 

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