binliu
Newbie level 4
Hi ,
I am using UVM 1.0 from Accellera and VCS vcs-mx-E-2011.03.
In my sequence, I have the following syntax
assert(req.randomize(clkgen) with {clock.period ==m_period ;});
However, I see print out m_period is correct ( a non zero number) but clock.period in item req is zero.
I have a timescale directives in uvm_users_pkg as timescale 1ns/1ps, but I use +override_timescale 1ps/1ps as VCS_OPT
this syntax works fine with mti, but doesn't work in VCS. and because this is a clock generator, all the clock has period as "zero" , and VCS stops because it detected infinite looｐ (of course).
Anyone has experience on this?
Thanks!
Bin
I am using UVM 1.0 from Accellera and VCS vcs-mx-E-2011.03.
In my sequence, I have the following syntax
assert(req.randomize(clkgen) with {clock.period ==m_period ;});
However, I see print out m_period is correct ( a non zero number) but clock.period in item req is zero.
I have a timescale directives in uvm_users_pkg as timescale 1ns/1ps, but I use +override_timescale 1ps/1ps as VCS_OPT
this syntax works fine with mti, but doesn't work in VCS. and because this is a clock generator, all the clock has period as "zero" , and VCS stops because it detected infinite looｐ (of course).
Anyone has experience on this?
Thanks!
Bin