Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Using very long path in MOS gate without current flow

Status
Not open for further replies.

protonixs

Full Member level 3
Joined
Jul 6, 2007
Messages
151
Helped
22
Reputation
44
Reaction score
7
Trophy points
1,298
Location
PH
Activity points
2,064
fact: there is no current flow in MOS gate.
so it is safe to use minimum metal width, am i right? my question is, is it safe if it takes very long path?
how about in a node where current flows, what are the considerations?
i think it is safe to use long paths as long as the width of the metal can carry the current flowing though it.
any comment will be appreciated.
 

Re: current and voltage

Hi ,
you have to take care about IR drop when u r routing a long current path

regards

analayout
 

Re: current and voltage

analayout said:
Hi ,
you have to take care about IR drop when u r routing a long current path

regards

analayout

isn't that IR dop is to be considered if you are considering voltage and not current.
 

Re: current and voltage

a antenna effect will be there.
Soln : - use the two metals layers
 

current and voltage

what is mean of " use the two metals layers " to avoid antenna effect
 

Re: current and voltage

Hi ,
if you are considering about vaoltage ie current is very small then IR drop will also be low

regards

analayout
 

Re: current and voltage

The mos gate has no DC current, but it has AC current flow when charge and discharge. And the long metal line cause a resistance connected to the gate, and this resistance combined with the parasitic capacitance from the gate to AC ground (such as the common source differential input pair) will cause some AC problems if it require high frequency performance. And also the metal line itself has its parasitic capacitance, which will also cause AC problems.


As for the anntena effect, it means if in your layout the mosfet gate is connected to a large area of metal 1, then in the etching process of the metal 1, large amount of charge will connected by this large area of metal 1 and cause a highvoltage on the mosfet gate, which will cause the gate oxide breakdown. So when layout , you can break the metal 1 and use metal 2 as a bridge over the metal 1, and thus avoid the high voltage on the mosfet gate.
 

current and voltage

you must consider the problem of speed
 

Re: current and voltage

Don't forget leakage current. Especially in 65nm.
 

Re: current and voltage

hhplay said:
Don't forget leakage current. Especially in 65nm.

How large is the typical leakage current in 0.18um technology?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top