library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity ram_mem is
generic (
data_size : integer := 12;
address_size : integer := 4
);
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector
);
end entity ram_mem;
architecture RTL of ram_mem is
type ram_type is array (2**address_size-1 downto 0) of std_logic_vector(data_in'range);
signal ram : ram_type := (others => (others => '0'));
signal read_address : std_logic_vector(address'range) := (others => '0');
begin
RamProc: process(clock) is
begin
if rising_edge(clock) then
if we = '1' then
ram(to_integer(unsigned(address))) <= data_in;
end if;
read_address <= address;
end if;
end process RamProc;
data_out <= ram(to_integer(unsigned(read_address)));
end architecture RTL;