Using .mif files for simulation

[Binome]

Hi,
I'm using vhdl to compute my design, Quartus II to synthesize it for a Cyclone IV FPGA and Modelsim to simulate it.
As I'm using M9K memory blocks I know they're starting from zeroes after synthesizing the design and downloading it to the FPGA but Modelsim doesn't know, it starts with Xs and all the results are false. I know I should use .mif files but I don't know what name to give them (I got several memories instanciated like that:

memory : for i in 0 to 7 generate
mem : ram_mem
...

) or where to place them.
I could do with a little help.
Thanks.

 

[TrickyDicky]

How are the memories generated? are they from megawizard/ipcatalog, or are they inferred?

 

[Binome]

They're inferred and my component is:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;

entity ram_mem is
  generic (
    data_size : integer := 12;
    address_size : integer := 4
    );
  port (
    clock   : in  std_logic;
    we      : in  std_logic;
    address : in  std_logic_vector;
    data_in  : in  std_logic_vector;
    data_out : out std_logic_vector
  );
end entity ram_mem;

architecture RTL of ram_mem is

  type ram_type is array (2**address_size-1 downto 0) of std_logic_vector(data_in'range);
  signal ram : ram_type := (others => (others => '0'));
  signal read_address : std_logic_vector(address'range) := (others => '0');

begin

  RamProc: process(clock) is

  begin
    if rising_edge(clock) then
      if we = '1' then
        ram(to_integer(unsigned(address))) <= data_in;
      end if;
      read_address <= address;
    end if;
  end process RamProc;

  data_out <= ram(to_integer(unsigned(read_address)));

end architecture RTL;

 

[TrickyDicky]

Here, your memory contents are already initialised to 0.

signal ram : ram_type := (others => (others => '0'));

The fact you are getting 'X' implies there is a problem elsewhere in the design.

 

[Binome]

That's what I just thought because of other simulations. Let's go on with my problem...

 

[TrickyDicky]

Have you accidently wired the multiple ram data busses together?

 

[K-J]

That's what I just thought because of other simulations. Let's go on with my problem...

read_address likely has unknown bit or bits. Either that or it's something that you haven't posted about here.
Kevin Jennings