kelvin_sg
Advanced Member level 4
I was implementing my design into Virtex 4 FPGA, there were a
module using 15 pieces of 8X8-bit multipliers which were originally
donw with DSP48s. The entire design uses
In an experiment I constrained this module's mult_style to LUT. As
expected the Number of DSP48s reduced by 15.
I am curious the final P&R report says
Timingwise, two implementations differ only by 0.04ns, I attribute it
to savings in routing.
module using 15 pieces of 8X8-bit multipliers which were originally
donw with DSP48s. The entire design uses
In an experiment I constrained this module's mult_style to LUT. As
expected the Number of DSP48s reduced by 15.
I am curious the final P&R report says
I like the result but how do I explain it? :?:
Timingwise, two implementations differ only by 0.04ns, I attribute it
to savings in routing.