Using HCT logic at below specified voltages

[Chris Z]

I have a series of latches attached to a 4.2 volt power rail. These need to be driven by a standard 3.3 microcontroller, with specified Voh of Vcc - 0.4v @ 1mA. So approximately 2.9v at low currents. There are scores of traces that will be affected by my decision. If I decide to use HC series logic for the latches, I will need a minimum Vih of 0.7 * 4.2v, or 2.94v, which might just barely work. Of course, placing external pullups on the lines will bring them all into spec, but this is an awful lot of pullups, increasing cost and board space.

Alternatively, I have considered using HCT logic for the latches. This would be a cheaper solution using less board space as well as being easier to route. The problem is that HCT is only specified to work down to 4.5v.

According to this appnote by TI, the reason for this is due to noise margin on Vil. (https://www.ti.com/lit/an/scla011/scla011.pdf) However, the analysis in that paper is all done assuming 5v signalling on the CMOS side. My thoughts are that since I am using 3.3v CMOS, the induced noise will be 2/3rds of that present at 5v, thus I should be able to tolerate a reduced noise threshold. Using HCT at sub specified voltages will allow me to run and meet all voltage tolerances without expensive pullup resistors.

Has anyone else ever tried this, and what was your result? Can I count on this being reliable in the field? This design is expected to ship several hundred thousand units a year, so while I am eager to find a solution that reduces the cost, I am not eager to do it if it means lower reliability and more returns.

Thank you for any advice.

Chris

 

[FvM]

The usage of pull-ups resistors seems pointless for a CMOS-to-CMOS interface as long as no additional loads come into play. It won't increase the noise voltage margin.

The comparision is between a guaranteed but small Vih margin of HC and an strictly viewn unspecified Vil margin of HCT. Because unloaded Vol of CMOS is effectively 0 V, HCT can be expected to give a positive worst case Vil margin. Typical margins can be expected in a similar order of magnitude.

I would probably prefer HC under the said conditions.

 

[Chris Z]

Thank you for your prompt reply. I am not quite certain what you are saying however.

Are you saying that pullups are not necessary, and that the HC logic at 4.2v with a required minimum Vih of 2.94 is still acceptable without pullups even though the spec for the microcontroller says Voh at 1mA is only 2.9 volts? I suppose this is possible, as nothing below 1mA is stated and I would expect it to rise slightly,, but the margin for this seems awfully low to me.

Or are you saying I have no choice but to use pullups and HC logic, and that the HCT idea won't work. Can you clarify just a little bit what you are advising?

Thanks again for your assistance.

P.S. You are correct that all loads on the line are CMOS. There are about 8-10 of them per trace. I do not know off the top of my head the leakage current on these (I will check this), but I would expect it to be in the nanoamp to microamp range.

 

[FvM]

In other words, I say that you should consider the properties of CMOS logic and make yor own conclusions.

One conclusion of mine is that pull-ups are useless in this case, CMOS Voh will be equal to Vdd without is well. Worst case Vih of HC will be achieved and thus the solution works without pull-ups.