I want to know that what is the exact method of getting a clock using DCM(Digital Clock Manager) for Xilinx Spartan 3 FPGA. Currently i am using ISE 6.0
Please define more clearly "getting a clock". There are different ways of using a DCM depending on what you need to do. Many designs don't need any DCMs.
You can use coregen to build a DCM core as yasser_shoukry suggested, or you can instantiate the DCM primitive directly into your HDL (see the DCM section of your ISE Libraries Guide).
I have used the core for "Single DCM" and added it into my project. But when i configure it on the Spartan 3, it uses it's default clock rather than the DCM component i have added.
How can i make it use the DCM generated clock instead of it's default clock?