Using DC to synthesis twice??

[swchen2002]

Hi all,
i have a question about using synopsys DC,
as i give constrain and optimal condition of a verilog design file,
then i synthesis it.
it has been mapped into gates, right? so i can see the slack timing report .

But if i start synthesis the mapped gated netlist again without modify
any constrain, and report timing again, then i get different slack timing!!

even third compile, i got another different slack timing report.


why is that?? Can't i compile the mapped gated??
i'm so confused!!

 

[ejean]

almost EDA algorithms are 'NP hard'
it means you may get different results in different machines, different platforms, different memory sizes, it is a 'relatively' optimized result, not 'absolutely'.

 

[linuxluo]

I think the difference of your result timing slack is not important, the important is is the result conform to your constraints every time you synthesis.
And now what you did is the first synthesis ,after you p&r, you should do the second synthesis because you will use the exact wire load model extracted from the layout of your circuit.

 

[skynet]

The DC give different time slack because each time the DC will place the component and different place, and the type of components use to map your design, for instance, for an AND gate, there are different kind of AND gate inside that technology library, so the DC sometime will pick different speed of AND gate and mapped into the logic. so u will get different time slack for different time u synthese your design. The most important thing is too meet ur design in timing analysis after P&R where the timing analysis is not that crusial as long that your P&R Engineer able to solve it in P&R process.

 

[linuxluo]

Hi, skynet
I think DC not place component, just translate and mapping. So the different of timing is due to DC using different component from the target library because NP complete in synthesis process.

 

[shockie]

i think that we would get the same results if we give the same conditions to Design Compiler. and i have done it .

 

[swchen2002]

almost EDA algorithms are 'NP hard'
it means you may get different results in different machines, different platforms, different memory sizes, it is a 'relatively' optimized result, not 'absolutely'.

thanks so much for your explain, here is another question
what does 'NP hard' means?? i never saw this phrase before.

thanks again!

 

[linuxluo]

Hi, Shockie
I think the same result means that the result timing is under your constraints, that's OK. But not means the detail circuit is the same between twice synthesis. In my design ,each time I find some difference can happen, but the function and timing is correct.

 

[jiang]

Hi, Shockie
I think the same result means that the result timing is under your constraints, that's OK. But not means the detail circuit is the same between twice synthesis. In my design ,each time I find some difference can happen, but the function and timing is correct.

we give the same constraint and then get the same result,
so ip vendor will provide systhesis script to guarantee you can get the same result.
you get the different results becouse you synthesis the circuit twice.

 

[linuxluo]

Hi, Jiang
Do you mean every time you synthesis your code in the same constraints you will get the absolutely same result?
If so, how you constraint your design ,I suppose ,in very detail?

 

[jiang]

all your commands in DC will be saved in command.log.
if you needed this constraint, you can modify command.log and save as script file.
you execute the script file in DC and get the same result eveytime.

 

[Nobody]

Set the link_library to the order { * ...... }
Then it will use the cach 1st . DC try to compile(optimize) design with multipl trials saved in local cach . Finally it chose the best result from cadidates . It have a lot memory requirement if you have very tie design and go many runs to look for optimization result .

 

[cnz]

Hi, Shockie
I think the same result means that the result timing is under your constraints, that's OK. But not means the detail circuit is the same between twice synthesis. In my design ,each time I find some difference can happen, but the function and timing is correct.

I agree with linuxluo!

Under the same constrainsts,you can get the same slack,however,the circuit is impossible equal between twice sysnthesis

 

[linuxluo]

Hi, Jiang
I don't agree your point. I think even if the design is under the same constraints you will get the different circuit. But if your design is simple you will get the same result but it rarely happen.

 

[ejean]

h**p://w*w*w.i*e*o*r.b*e*r*k*e*l*e*y.e*d*u/~hochbaum/html/book-aanp.html

NP-hard is not NP-complete, but it's 'hard' to solve. In other words, it's a very high BigO algorithm problem.
To solve such kind of problem, we need some 'heuristic'. It need a 'seed', from the seed(an initial value), we can reach a merely relatively optimized result, just as routing, floorplanning, and etc. But it's very difficult to get the absolutely optimized result when the design enormous increasing. We need the 'trade-off' between speed and size, speed and power, and so on. That's why a delicated design so hard.

 

[aramis]

h**p://w*w*w.i*e*o*r.b*e*r*k*e*l*e*y.e*d*u/~hochbaum/html/book-aanp.html

NP-hard is not NP-complete, but it's 'hard' to solve. In other words, it's a very high BigO algorithm problem.
To solve such kind of problem, we need some 'heuristic'. It need a 'seed', from the seed(an initial value), we can reach a merely relatively optimized result, just as routing, floorplanning, and etc. But it's very difficult to get the absolutely optimized result when the design enormous increasing. We need the 'trade-off' between speed and size, speed and power, and so on. That's why a delicated design so hard.

Thanks for your explain!!

 

[vsop]

As long as you keep the same design data base & working environment, you will get the same results. The design data base means your design source codes, constraint script, the working environment means the DC version. You can make a trial: change the typing order of your codes, you will get the different results unless your design is small. Buy you can get the equivalent results in the above case.
The reason for getting different design is DC is starting from the different design, even though they are equivalent design.

 

[linuxluo]

Hi, vsop
I still insist on my original opinion. Even if the same typing order ,same source file ,same DC version, same environment and the same constraints, but if your design is not little, you will fine the results you got is different . But in many cases, the results can be conform the constraints.