Using bus in process sensitivity list

[anbu1231]

I am a newbie to VHDL.. i searched lot to get an answer but in vain so posting here.. Sry for the long post..

I have three inputs to show in the seven segment.. In basys board, since the seven segment cathodes are tied together, i am using a 2-bit selection to choose where to display the data.

my inputs are 5-bit bus (DB), 1-bit (A), 1-bit (B). I tried many options to set the value for the selection bit. I used all three inputs in a single process which is wrong since I cant use multiple event checks and i cant event check data change in the bus.

Then I used three processes but it dint synthesize. Cannot update a signal from different processes.

So, I created another process with three signals (counters) in its sensitivity list. These are 1-bit counters which are incremented in the processes (the inputs processes). Hence the counters will toggle (basically) and based on the toggle I updated the value of the selection bit in my fourth process.

This works fine with the processes having the bit signal inputs (A, B). But in the process with bus input, the counter value is not incremented. It remains zero all time. I have the code like this for that process

signal Cnt1 : std_logic_vector (0 downto 0) := "0";
signal op : std_logic_vector (4 downto 0);
Process(DB)
begin
case DB(0) is
when '0' ...
when others ...
end case;

op1 <= DB(3 downto 0);

cnt1 <= cnt1 +1;
end process;

the case is executing, the value is set to op1 but the cnt1 is not incremented. I dont know why? Also, i would like to know how to detect the change in bus data (inside the process).. I searched for it but no help.

If there is any other simple way to get the whole thing done, plz let me know..

Thnks in advance..

 

[FvM]

Sensitivity lists in VHDL are often misunderstood. Actually, they are meaningless in synthesized VHDL. You can't count events like
you did in your code. A HDL counter needs an edge sensitive condition, which is the equivalent of a hardware counter.

 

[anbu1231]

got that.. thnks..

now, what should I do implement my request? is there any function to check the data change or event occurrence in a bus (similar to rising_edge, falling_edge for signals)?

 

[FvM]

is there any function to check the data change or event occurrence in a bus

Go for synchronous edge detection: Sample the input in a clocked process, check for the changes.

 

[anbu1231]

FvM, Thank you very much.. it worked out fine...