Using buffer and shifting in VHDL problem

[ghattas.akkad]

Hello
I am having trouble shifting a Buffer std_logic_vector as it is not shifting and updating the results
the expression is:

denominator: buffer std_logic_vector(M downto 0);
if(clk'event and clk='1') then		

   if(sld='1') then
      op_denom<=denominator(M-1 downto 0)&'0';
   end if;
end if;

I am using a buffer on denominator and numerator for continuous shifting and storing I will have to check Numerator MSB and Denominator MSB and stop until they are '1'

MSBone <= denominator(M) and numerator(M);

But in simulation the denominator is not shifting even thought the sld bit is set

 

[std_match]

Why should denominator shift? You are not assigning anything to it.
Avoid using "buffer". You will get into trouble when doing larger designs. Use intermediate signals instead.

 

[ads-ee]

denominator <= denominator(M-1 downto 0)&'0';

would be shifting the denominator signal what you were doing is assigning the shifted value of the denominator signal to op_denom, which is completely different.

 

[ghattas.akkad]

Thank you I will stop using the buffer as well