Hmm...
Typos in this code, missing module name, missing begin, also mixed case (carpel tunnel inducing shift key), along with antiquated Verilog port declarations. All bad coding habits IMO.
I'm wondering why you have "
sync_rst & T_reg"? The only way the T_reg will work is if the reset is active (assuming sync_rst is active high given the ! in front). Also not sure why you would add an inverter to the rest path to make your reset negedge is that due to there only being active low reset Flip-Flops in the library?
You really want | instead of & if you want T_reg to reset the Out FF.
This circuit makes me cringe though, but maybe it's standard practice in ASIC design nowdays?
If all you wanted to do was clear Out 1 clock cycle after T goes high, i.e. only have Out update once at the leading edge of T and get cleared on the next clock cycle.
Code Verilog - [expand] |
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| assign int_rst = !sync_rst;
always @(posedge clk or negedge int_rst)
if (!int_rst) Out <= 1'b0;
else if (T && !T_reg) Out <= In;
else if (T_reg) Out <= 1'b0; |