Using an older Quartus version

[shaiko]

Hello,

A working Quartus project has synthesized with version 14.
I'm trying to resynthesize the project with version 13 - compilation is successful, however the design fails to work.

What should I look into to fix the problem?

 

[TrickyDicky]

Something like this could easily be a timing problem.
Check that it meets timing in both. as the algorithms often change from one version to the next, the fitter can place the logic in completly different plces.

Does it have async logic? does it have a full list of timing specs in the SDC.

Where is it the design failing? internally or on an IO (again - this can be timing related).

 

[shaiko]

The design has lots of sh** it shouldn't have. You can write a book about it and call it: "designing FPGAs the wrong way".

And no, I haven't done any timing analysis on it.

Have you ever encountered a problem as such that turned out to be not timing related?
note: it does make use of a PLL IPs...

 

[TrickyDicky]

Have you ever encountered a problem as such that turned out to be not timing related?
note: it does make use of a PLL IPs...

PLLS are not a magic bullet. Used wronly they can be bad.

A design that has full timing specs should work in all versions of the tool (assuming constraints met). The only time Ive seen a problem was down to a synth bug (which exists in the latest ISE - so it will never be fixed asside from a patch). This is the only synth bug I have ever seen.

Asside from that - I have seen plenty of old poor designs that fail from one version to the next. The answer was usually "Stick with the working version". Even worse is when it works for some compiles and not on others, because of the changes in fit seed causing timing to fail (there were no constraints).

Basically - no timing constraints - stick with the tool version that "works".
Or improve the design.

No other options really.

 

[shaiko]

I agree with your approach.
With that said, I have a strong filling that timing isn't the trouble maker in this case.

Just completed the following test:

Step 1. On a PC with V14.0 I compiled the design and converted the SOF file to JIC (on the same V14 machine) - design works.
Step 2. On a PC with V13.1 (same source files) I compiled the design, converted the SOF file to JIC - design doesn't work.
Step 3. I took the SOF file generated from the PC with V13.1 and converted it to JIC on the PC that runs version V14 (the PC from step 1) - design works.

Clearly, the issue here is the SOF -> JIC conversion process when done on the V13.1 machine.
However, the file conversion settings are absolutely the same on both PCs!
Unless it's a Quartus bug - I'm really baffled...

- - - Updated - - -

And as with most of my IDE frustrations - this one also ends with a simple google search.
http://www.cubiccyclonium.org/support/kdb/solutions/rd10162014_566.html