[SOLVED] using a verilog keyword in rtl

[fragnen]

The Verilog has a keyword posedge. Can poedge be used as the the name of one of the input pins of a module in a rtl as below? Can a parameter named posedge be used as shown below in a rtl? Please reply.

module adder (posedge, in1, out1);
input posedge;
input in1;
output out1;
.......
.......
endmodule

module subt( in3, in4, out2....);
parameter posedge;
input in3, in4;
output out2;
.........
.........
endmodule

 

[dave_59]

No.

 

[fragnen]

Will there be any drawback if such a rtl is synthesized and already send for tapeout?

 

[dave_59]

It is not legal, so there is no guarantee how downstream tools will support it.

 

[ads-ee]

The "posedge" in the code must have been mixed case or all uppercase in the HDL code that was synthesized, p&r, an taped out. Otherwise it wouldn't have successfully been taped out.

The Verilog keyword is "posedge" (all lowercase); POSEDGE, PosEdge, etc are NOT keywords. It is a very poor practice to use keywords in such a fashion.

 

[barry]

Sorry, but this is just a stupid question. There are an infinite number of words that are NOT keywords; just use one of those.

 

[rca]

what is the value to reuse keyword, the human is enough clever to create new name.

 

[danadakk]

Verilog keywords (it is case sensitive) :

https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/Verilog-Reserved-Keywords

Regards, Dana.