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using 2bit data with OSERDESE3

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Newbie level 4
Nov 12, 2021
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Dear All,
I need your help in something related to serializing data in ULTRASCALE_PLUS FPGA.
My design has a 2bit data derived with the system clock 40Mhz and I would like to serialise it with 80 Mhz clock. I noticed that Kintex ULTRASCALE_PLUS uses OSERDESE3
IP and unfortunatly , it accepts only DATA_WIDTH with size 8 !..How can my 2bit data fit into this requirement?

I would use FIFO with different input and output widths and clocks.
FIFO In: 2 bit@40 MHz
FIFO Out: 8 bit@10 MHz

FIFO Out would go to OSERDESE3 as input.

Note that OSERDESE3 could have DATA_WIDTH = 4 or 8 -> XAPP1324 (v1.1) August 23, 2018, page 9.

@qamesh ,
IP and unfortunatly , it accepts only DATA_WIDTH with size 8 !..How can my 2bit data fit into this requirement?

What is stopping you to do a padding of the MSBs like this.....

oserdes_data <="000000" & my_2bit_data;


I had the same idea as dpaul. .. but then I read "with 80MHz clock"
This won´t work for 8 bits.
But I guess this does not even work for serdes with 2 bits x 40MHz. Because SERDES needs some overhead for clock recovery and so on.

But I´m not experienced with serdes.


You are using a Xilinx part, they have an ODDR primitives you could use, that would make things simple.

an ODDR has two data inputs and outputs one data output when the clock is high and the other when the clock is low. Therefore you can connect the two bits to each data input and the 40 MHz clock to the clock input and the output will be at an 80 Mbit data rate.

you could use an oserdes, but that is overkill and is typically used to achieve serial rates up to Gbit range. To use the oserdes you could load an 8-bit register with four 2-bit values (10 MHz rate, i.e. 40 MHz/4) and then load that 8-bit value into the oserdes to output a 80 Mbit., but why do all that when the ODDR would be far easier to implement.
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