I feel tempted to mention that we don't like pure link answers at Edaboard.
djnik1632 is asking a specific question and the link doesn't actually answer it. I believe that the link gives a basic explanation about multiple clock domain setups, but the OP is asking about a best solution for the said frequency combination.
- - - Updated - - -
You might find out that 50/18.432 = 128*9/3125. A special PLL would be able to derive one from the other clock. But in your design, they have to be treated as asynchronous clocks anyway. In so far, it's not important from the domain crossing viewpoint, if they are sourced from different clock oscillators which is probably the most simple solution.