use of gates in cells of fpga

[priyankadarkunde]

in fpga when gates in one cell are used completely, it switches to other cell and uses gates available in that cell. i want to know when it shows the gate count does it include all gates in that other cell or it includes only used cell in gate count??

 

[TrickyDicky]

There are no gates in an FPGA, so there is no gate count. And therefore a cell cannot be full of gates.

An ALUT (altera) or Slice(Xilinx) contains and LUT and a register (and some other little bits). But theres not gates. They are created by setting the LUT to a specific table.